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Upcoming Events

Wednesday 25th April 2012 - 6pm MWB Edinburgh, 9-10 St. Andrew Square

Gerard Wimpenny | Nujira

Designing for the RF section of handsets takes specialist RF knowledge.

Designing a handset power supply IC which can track the full 20MHz bandwidth of LTE modulation schemes and do it with high efficiency and low noise takes a specialist combination of RF systems, power management and high performance analog skills. Cambridge and Edinburgh based Nujira has taken its broadcast and infrastructure experience in envelope tracking power modulators and applied it to the handset market. The talk will discuss handset RF architectures, historic and future and where power management fits into these architectures. Envelope tracking is a disruptive technology that needs a system implementation with the platform transceiver and baseband chipset. The talk will describe how efficiencies of RF power amplifiers (PA) can be dramatically improved especially on high Crest Factor signals and will talk further through the network benefits that can be realised by linearizing the PA and increasing its output power capability. The talk will also describe the systems and design engineering structure that was developed to translate a disruptive RF systems concept into an analog/power management IC.

Past Events

17th of November 2011

Jed Hurwitz | Metroic

Nanometer analog layout

A critical aspect to achieving the theoretical performance of an analog circuit has for a long time been its layout. Perhaps more importantly, when the layout fails to match the design, the project can fail in schedule, cost, or performance. There are many layout-induced effectsin nanometer CMOS that alter the transistor characteristics, and this means that matching the layout to the design is becoming more difficult and critical. This tutorial provides an overview of those effects, and provides some strategies and approaches to combat them. Even if you don’t do the layout yourself, every designer should be able to guide the process through to success.

14th of December 2009

Kofi Makinwa | Delft University of Technology

Designing Smart Sensors in Standard CMOS

Smart sensors are systems in which sensors and dedicated interface electronics are integrated on the same chip, or at least in the same package. Due to the low-level analog output of typical sensors, designing interface electronics that "does no harm," i.e. does not impair sensor performance, is quite challenging, especially in today's mainstream CMOS technology, whose inherent precision is limited by 1/f noise and component mismatch. However, since most sensors are quite slow compared to transistors, dynamic techniques can often be used to trade speed or bandwidth for higher precision. Examples of such techniques are auto zeroing, chopping, dynamic element matching, switched-capacitor filtering and sigma-delta modulation. This talk describes the use of such dynamic techniques in the design and realization of state-of-the-art smart CMOS sensors for the measurement of temperature, wind velocity and magnetic field.

15th of September 2008

Willy Sansen | President of Solid-State Circuits Society

Analog Design in nm CMOS

A special presentation from Willy Sansen, President of Solid-State Circuits Society, and Professor at KULeuven (Katholieke Universiteit Leuven). He will be presenting an overview of IEEE, and the Solid-State Circuits Society, followed by an short course on Analog Design in nm CMOS extracted from his latests course book 'Analog Design Essentials'.

26th of August 2008

Ken Kundert | Designer's Guide

Verification of Complex Analog Integrated Circuits

Verification is becoming widely recognized as one of the most important issues when designing large complex analog and RF mixed-signal circuits. As a result, design methodologies are starting to change. This change mirrors a change that occurred in digital design 10-15 years ago. In this presentation I will show why the problem has become so significant, and what people are doing to control the problem. This presentation is targeted for design management, design engineers, and verification engineers. It outlines a practical and proven methodology for performing the complete functional verification of the most complex analog SoCs using examples to illustrate the essential points. This methodology not only assures that the implementation is functionally consistent that is shown through exhaustive transistor-level testing to be functionally equivalent to the implementation. Use of this methodology also leads naturally to the adoption of a top-down design style and aids performance verification. .